High performance ECC circuits

Conventional ECC circuits rely on logic calculations that lead to complex routing in circuit layouts. The delay in these circuits is typically constrained by the RC delay of the metal lines. Additionally, conventional ECC circuits occupy significantly more area than logic circuits of equivalent gate count due to the complex routing. They also require a large number of test vectors to achieve sufficient test coverage.

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UniRAM's ECC circuit architectures address these challenges by arranging logic calculations in a rotational configuration, dramatically simplifying the routing of ECC circuits. This innovative approach offers several key advantages:

• Reduced area.

• Faster performance: all routing consists of short lines, achieving speeds of approximately five gate delays.

• Consistency: the speed of a 1024-bit ECC circuit matches that of a 64-bit ECC circuit.

• Expandable and scalable: the same circuit unit designed for a 64-bit ECC can be expanded for 1024-bit or larger.

• Efficient test coverage: a small number of test vectors can comprehensively cover wide ECC circuits.